Electrical devices, which may be boards, ICs or embedded cores within ICs, use JTAG interfaces to provide for testing and debugging of the device's hardware and software designs. In the past, device test and debug interfaces used the full pin JTAG interface consisting of a TDI, TCK, TMS, TDO, and an optional TRST pin. More recently, reduced pin JTAG interfaces are being developed and used for test and debug when device pins are not available for the full pin JTAG interface. Some known reduced pin JTAG interfaces include; (1) a simultaneously bidirectional transceiver (SBT) based reduced pin JTAG interface described in a 2006 International Test Conference paper by Whetsel which is incorporated by reference herein, (2) an IEEE standard P1149.7 described in a white paper which is incorporated by reference herein, (3) a JTAG Link (JUNK) interface developed by DebugInnovations which is incorporated by reference herein, and (4) a single wire JTAG (SWJ) interface developed by ARM Ltd which is incorporated by reference herein. Reducing the number of JTAG pins, while enabling access to pin limited device, brings about a reduction in the communication bandwidth between a JTAG controller and JTAG device. The disclosure describes a JTAG interface based on double data rate circuitry that reduces JTAG pins while advantageously maintaining a high communication bandwidth between a JTAG controller and JTAG device. The double data rate JTAG interface may be used for device test, debug, programming or other operations performed today by the JTAG bus.
FIG. 1 illustrates an example of a full pin JTAG interface bus 102 coupled between a JTAG TAP controller 104 and JTAG TAP domain 106 within a device 108. The TAP domain is an IEEE 1149.1 based architecture that includes a TAP state machine, an instruction register, and plural data registers. The TAP domain 106 may be used for testing, debugging, or programming of the device 108. The full pin JTAG (IEEE 1149.1) interface 102 comprises a TDI, TCK, TMS, TDO and optionally a TRST signal. Pull up (PU) elements 105 are required on the TDI and TMS inputs of the device 108 to pull these signals high if they are not externally driven by the controller 104. Pulling TMS high causes the TAP state machine of the TAP domain 106 to remain in the Test Logic Reset state of FIG. 12A. If the optional TRST signal is not used, a power up reset (POR) circuit 110 may be used in the device 108 to reset the TAP domain when the device powers up. The device's TAP domain 106 can also be reset by an input sequence from the TAP controller 104 on bus 102.
Timing diagram 110 illustrates the operation of JTAG bus 102 during a scan operation. As seen, the TAP controller 104 outputs TDI and TMS signals to the TAP domain 106 on the falling edge 114 of the TCK and the TAP domain samples the TDI and TMS signals on the rising edge of the TCK 116. The TAP domain 106 outputs the TDO signal to the TAP controller 104 on the falling edge 114 of the TCK and the TAP controller samples the TDO signal on the rising edge 116 of the TCK. The timing operation of the JTAG bus 102 between the TAP controller 104 and TAP domain 106 1 is well known and broadly used in the industry for serially accessing devices for test, debug, programming and/or other operations.
FIG. 2 illustrates an example of a double data rate (DDR) circuit 202 interfaced between a sending circuit 204 and a receiving circuit 206. The DDR circuit 202 comprises flip flops 208-214 arranged as shown. The sending circuit 204 outputs an A/B data signal and a clock signal to the DDR circuit 202. The clock signal output from the sending circuit 204 is also input to the receiving circuit 206. The data inputs of Flip flops 208 and 210 are coupled to the A/B data output signal from sending circuit 204 and their clock inputs are coupled to the clock output signal from sending circuit 204. The data input of flip flop 212 is coupled to the data output of flip flop 208 and the data input of flip flop 214 is coupled to the data output of flip flop 210. The clock inputs of flip flops 212 and 214 are coupled to the sending circuit's clock output signal.
As seen in timing diagram 216, the sending circuit outputs serial A 218 and B 220 data components on the A/B signal to the DDR circuit 202 during each clock output signal 228-236. Flip flop 208 stores the A data component 218 during the rising edge 224 of the clock signal 222 and flip flop 210 stores the B data component 220 on the falling edge 226 of the clock signal 222. The A data component 218 and B data component 220 stored into flip flops 208 and 210 are transferred into flip flops 212 and 214, respectively, on the rising edge 224 of the next clock period 230. The A and B data components stored into flip flops 212 and 214 are transferred into the receiving circuit 206 on the rising edge 224 of the next clock signal 232. This process of serially inputting A and B data components from the A/B signal output from the sending circuit 204 followed by outputting the A and B data components in parallel to the receiving circuit 206 is repeated during the operation of the DDR circuit. DDR circuits are high speed circuits and can transfer data well above 100 MHz.
As will be described below, the disclosure takes advantage of the high speed DDR circuit's ability to serially input two data components, A 218 and B 220, from a single output of a sending circuit during the rising 224 and falling 226 edges of a first clock signal 228 respectively, separate and output the A and B components during the rising edge 224 a second clock signal 230, and input the separated A and B components in parallel to a receiving circuit on the rising edge 224 of a third clock signal 232.